// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hiddrphy_dx_static_reg_reg_offset.h
// Project line  :  IP
// Department    :  
// Author        :  Jason, Edward
// Version       :  .1
// Date          :  2011/11/29
// Description   :  The DDR PHY Controller Block
// Others        :  Generated automatically by nManager V4.2 
// History       :  Jason, Edward 2018/03/19 12:28:13 Create file
// ******************************************************************************

#ifndef __HIDDRPHY_DX_STATIC_REG_REG_OFFSET_H__
#define __HIDDRPHY_DX_STATIC_REG_REG_OFFSET_H__

/* HIDDRPHY_DX_STATIC_REG Base address of Module's Register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE                       (0x1000)

/******************************************************************************/
/*                      PHY_Controller HIDDRPHY_DX_STATIC_REG Registers' Definitions                            */
/******************************************************************************/

#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXPHYCTRL_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x200) /* DX PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL_REG             (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x204) /* IO control register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DQSSEL_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x208) /* Swap of DQ in PHY */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNCKCTRL_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x20C) /* This register is for PLL phase select within the PHY. And should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_PHYPLLCTRL_DX_REG     (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x210) /* PHY PLL control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_PHYCTRL2_REG          (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x214) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL1_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x218) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL2_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x21C) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_PHYPLLCTRL_DX2_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x220) /* PHY PLL control register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_PHYPLLCTRL_DX3_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x224) /* PHY PLL control register 3 */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL6_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x228) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNCLKBDL_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x230) /* DATA block clock bit delay line setting */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC5_0_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x22C) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC5_1_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2AC) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_PHYCTRL0_0_REG        (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x234) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_PHYCTRL0_1_REG        (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2B4) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL0_0_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x238) /* Data block PHY miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL0_1_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2B8) /* Data block PHY miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL7_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x240) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL1_0_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x264) /* Data block PHY miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL1_1_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2E4) /* Data block PHY miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXDEBUG0_0_REG        (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x23C) /* Data block PHY debug signals */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXDEBUG0_1_REG        (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2BC) /* Data block PHY debug signals */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXPHYRSVD_0_REG       (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x244) /* Data block PHY reserved control pins. This register is for PHY control and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXPHYRSVD_1_REG       (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2C4) /* Data block PHY reserved control pins. This register is for PHY control and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL2_0_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x248) /* Data block PHY miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL2_1_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2C8) /* Data block PHY miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXDEBUGCONFIG_0_REG   (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x24C) /* Data block PHY debug/miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXDEBUGCONFIG_1_REG   (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2CC) /* Data block PHY debug/miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC_0_REG          (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x250) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC_1_REG          (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2D0) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL3_0_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x254) /* Data block PHY debug/miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL3_1_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2D4) /* Data block PHY debug/miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL4_0_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x258) /* Data block PHY debug/miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNMISCCTRL4_1_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2D8) /* Data block PHY debug/miscellaneous control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL3_0_REG          (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x25C) /* IO control register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL3_1_REG          (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2DC) /* IO control register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL8_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x260) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC1_0_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x268) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC1_1_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2E8) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC2_0_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x26C) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC2_1_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2EC) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC3_0_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x270) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC3_1_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2F0) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC4_0_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x274) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXNDCC4_1_REG         (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2F4) /* Data block PHY DCC control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_BYP_CK90_CODE_0_REG   (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x278) /* Bypass mode delay line code */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_BYP_CK90_CODE_1_REG   (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2F8) /* Bypass mode delay line code */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_BYP_CK90_CODE_2_0_REG (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x27C) /* Bypass mode delay line code shadow register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_BYP_CK90_CODE_2_1_REG (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x2FC) /* Bypass mode delay line code shadow register */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL9_REG            (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x280) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_IOCTL10_REG           (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x284) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXCTL_PHASE_REG       (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x288) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_RESERVED_3RD_REG      (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x28C) 
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DUMMY_IOCTL_DUTY_REG  (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x290) /* dummy ioctl duty */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXCTL_MISCCTRL_REG    (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x294) /* dxctl misctrl */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXRSVD1_REG           (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x298) /* DX RSVD Register1 */
#define PHY_Controller_HIDDRPHY_DX_STATIC_REG_DX_DXRSVD2_REG           (PHY_Controller_HIDDRPHY_DX_STATIC_REG_BASE + 0x29C) /* DX RSVD Register2 */

#endif // __HIDDRPHY_DX_STATIC_REG_REG_OFFSET_H__
